Advanced Packaging

Advanced packaging is the semiconductor route highlighted in EP270 一枚芯片的漫长征途：我们离“算力自由”还有多远？ as one of China’s relatively stronger catch-up areas. Packaging protects chips, connects them electrically to the outside world, and increasingly affects system performance when AI workloads need fast data movement between processors and memory.

The episode links advanced packaging to HBM and the memory wall. Stacking memory, shortening connections, and improving chip-to-chip links can raise effective bandwidth when raw process scaling is harder. At the same time, the source cautions that packaging is not an independent shortcut: it needs enough advanced wafers, materials, equipment, and production volume to matter economically.

E230｜1万亿收入预期背后：英伟达的巅峰与软肋 adds advanced packaging as a gating constraint for Nvidia’s order narrative. 肖志斌 / Xiao Zhibin says 3 nm wafer supply may be easier to reason about than CoWoS-style packaging capacity, while Intel EMIB, Samsung, and TSMC are discussed as possible but constrained alternatives or complements.

华为的「韬定律」，是创新还是噱头？｜ Bonus adds a Huawei-specific caveat: packaging is necessary for three-dimensional routes, but the most ambitious Cell-to-Cell Logic Stacking version cannot be evaluated as a packaging claim alone. It would also require upstream EDA changes and a design flow that can plan logic cells vertically before packaging.

E228｜谷歌TPU能撼动英伟达吗？前TPU工程师首次揭秘 adds the TPU ramp version. Henry says Google and Broadcom still rely on TSMC CoWoS-style packaging to combine High Bandwidth Memory and compute dies, so TPU external expansion faces the same back-end capacity and yield questions as other advanced AI accelerators.

Key Claims

• Packaging has moved from a lower-visibility back-end step toward a performance-critical AI infrastructure layer.
• China’s relative gap is described as smaller in packaging than in advanced lithography or leading-edge wafer fabrication.
• Earlier acquisitions and industry funding helped domestic packaging firms absorb advanced packaging capability.
• Packaging helps only when matched with suitable chips and memory; applying advanced packaging to much older nodes may not create meaningful performance gain.
• In high-end AI systems, packaging capacity can decide whether accelerators and HBM become deliverable systems rather than separate components.
• For Tau Law, advanced packaging is only one layer of proof; the source also asks whether design tools, verification, power, yield, and cost can support cell-level logic folding.
• TPU scaling shows that packaging capacity is not only a Nvidia issue; specialized accelerators also need advanced package integration before they become deployable pod-scale systems.

Connections

• JCET / 长电科技 — packaging company and factory visit in the source.
• High Bandwidth Memory, Memory Wall, and Semiconductor 3D Stacking — performance and architecture context.
• TSMC — existing wiki page where advanced packaging also appears as an HBM and CoWoS-style bottleneck.
• Domestic AI Chip Catch-Up and Semiconductor Supply Chain — domestic strategy and chain context.
• Nvidia Blackwell Platform, Nvidia Vera Rubin Platform, Intel, and Samsung - E230’s platform-supply and packaging-alternative context.
• Tau Law, Cell-to-Cell Logic Stacking, and Electronic Design Automation — Huawei bonus episode’s distinction between packaging and design-flow readiness.
• TPU, Broadcom, TPU Pod System Optimization, and AI Hardware Supply Chain Pressure - E228’s TPU packaging and supply-ramp branch.