CXL Memory Pooling

CXL Memory Pooling is the Google-linked architecture discussed in 存储三巨头破万亿市值，存储超级周期何时能见顶？｜ S10E13. The source describes it as using CXL to make DRAM available as a pooled TB-scale resource, improving utilization when memory capacity is scarce or unevenly used.

The episode contrasts this with Nvidia’s NAND+DPU direction. Google-style DRAM pooling is described as TB-scale, while Nvidia’s NAND route is PB-scale; the difference means they solve different hierarchy problems and neither should be read as proof that HBM disappears.

Key Claims

• CXL pooling can improve DRAM utilization by making memory capacity more flexible across systems.
• DRAM pools occupy a different layer from NAND storage and High Bandwidth Memory.
• Better utilization can reduce waste while still allowing total demand to grow if AI workloads expand.
• CXL pooling is one route through the Memory Wall, not a universal replacement for accelerator-adjacent memory.

Connections

• Google and TPU - platform context for the source’s example.
• AI Data Center Memory Hierarchy and Memory Wall - architecture context.
• High Bandwidth Memory, Agent-Era NAND Storage, and High Bandwidth Flash - adjacent memory layers and routes.
• Jevons Paradox In AI - efficiency can coexist with rising total demand.