Electronic Design Automation

Electronic Design Automation, or EDA, is the chip-design software toolchain discussed in EP270 一枚芯片的漫长征途：我们离“算力自由”还有多远？. The episode describes it as a “mother of chips” layer because modern chip engineers use software to describe hardware, simulate behavior, verify designs, and prepare files for fabrication.

The source emphasizes that EDA is not one program. It is a deep suite of tools and flows shaped by decades of customer feedback, process compatibility, and edge-case handling. This makes global incumbents such as Synopsys / 新思科技, Cadence Design Systems / 楷登, and Siemens EDA / 西门子EDA hard to replace even when domestic chip-design talent improves.

Key Claims

• EDA dependence sits upstream of wafer manufacturing, so chip self-reliance cannot be measured only by fab capacity.
• Strong EDA tools reduce but do not eliminate [[TapeOutRisk|tape-out risk]] because large chips have too many states for complete pre-silicon certainty.
• Customer feedback and process-node compatibility create compounding advantages for incumbent EDA vendors.
• Domestic AI-chip firms need usable software design flows as well as access to [[SMIC|SMIC-like]] manufacturing and downstream software ecosystems.

Connections

• Synopsys / 新思科技, Cadence Design Systems / 楷登, and Siemens EDA / 西门子EDA — main global vendors named in the source.
• Semiconductor Supply Chain — design layer where EDA sits.
• Tape-Out Risk — practical failure mode EDA tries to manage.
• Domestic AI Chip Catch-Up — domestic replacement and self-reliance context.