Electronic Design Automation

Electronic Design Automation, or EDA, is the chip-design software toolchain discussed in EP270 一枚芯片的漫长征途：我们离“算力自由”还有多远？. The episode describes it as a “mother of chips” layer because modern chip engineers use software to describe hardware, simulate behavior, verify designs, and prepare files for fabrication.

The source emphasizes that EDA is not one program. It is a deep suite of tools and flows shaped by decades of customer feedback, process compatibility, and edge-case handling. This makes global incumbents such as Synopsys / 新思科技, Cadence Design Systems / 楷登, and Siemens EDA / 西门子EDA hard to replace even when domestic chip-design talent improves.

华为的「韬定律」，是创新还是噱头？｜ Bonus adds a concrete future-tooling case through Tau Law. Zhang Haijun / 张海军 argues that full Cell-to-Cell Logic Stacking would require new EDA flows because three-dimensional logic placement has to be considered during design, routing, and verification rather than added only through back-end packaging.

真正改变世界的技术，为什么一开始都不被看好？| S10E16 adds the historical absence of commercial EDA as one reason early dense integration looked unrealistic. The same episode brings EDA into the AI era: AI can help write or check simple bounded digital modules, but new process-specific effects and undefined design-tool problems still require domain know-how.

Key Claims

• EDA dependence sits upstream of wafer manufacturing, so chip self-reliance cannot be measured only by fab capacity.
• Strong EDA tools reduce but do not eliminate tape-out risk because large chips have too many states for complete pre-silicon certainty.
• Customer feedback and process-node compatibility create compounding advantages for incumbent EDA vendors.
• Domestic AI-chip firms need usable software design flows as well as access to SMIC-like manufacturing and downstream software ecosystems.
• Cell-level three-dimensional logic folding would extend the EDA problem from ordinary chip layout into a more complex vertical-design and verification space.
• S10E16 adds that missing design tools can make a future trajectory look impossible before the toolchain catches up.
• AI assistance can cover bounded design tasks, but the source keeps novel EDA and process interactions inside human engineering judgment.

Connections

• Synopsys / 新思科技, Cadence Design Systems / 楷登, and Siemens EDA / 西门子EDA — main global vendors named in the source.
• Semiconductor Supply Chain — design layer where EDA sits.
• Tape-Out Risk — practical failure mode EDA tries to manage.
• Domestic AI Chip Catch-Up — domestic replacement and self-reliance context.
• Tau Law, Huawei, Zhang Haijun / 张海军, and Cell-to-Cell Logic Stacking — source case where EDA readiness is the boundary between a metric and a manufacturable design flow.
• Wang Bo / 汪波, Moore’s Law, System-Level Semiconductor Optimization, and Domain Know-How Moat — S10E16’s history-to-AI design-tool extension.