Photolithography Bottleneck

Photolithography bottleneck is the semiconductor-manufacturing constraint explained in EP270 一枚芯片的漫长征途：我们离“算力自由”还有多远？. The episode describes lithography as the process of patterning circuitry onto wafers through photoresist and exposure, and presents [[ASML|ASML / 阿斯麦]] as the key supplier for the highest-end EUV systems.

The source’s main caution is that lithography should not be treated as the whole problem. Advanced process manufacturing also depends on materials, inspection, other equipment, process control, cleanrooms, water and gas purity, yield, and scale experience. The bottleneck is therefore a cluster, not a single-machine story.

Key Claims

• EUV access is strategically important for leading-edge chips, but access to equipment does not automatically create cost-effective manufacturing.
• Mature-process chips and frontier AI accelerators have different lithography and process requirements, so “chip” is too broad for one difficulty label.
• Workarounds using older lithography can increase process steps, lower yield, and raise cost even when a chip can technically be produced.
• The bottleneck gets sharper as [[MooreLaw|Moore’s Law]] reaches physical and economic limits.

Connections

• ASML / 阿斯麦 — central equipment supplier named in the episode.
• TSMC, Samsung, Intel, and SMIC — manufacturers discussed around advanced process capability.
• Semiconductor Supply Chain and AI Hardware Supply Chain Pressure — broader constraint structure.
• Domestic AI Chip Catch-Up — China-focused substitution context.