Scale Up AI Interconnect

Scale Up AI interconnect is the low-latency, high-bandwidth connection layer that lets many AI accelerators operate as one software-visible domain. In 国产 AI 算力能凭「超节点」弯道超车吗？｜WAIC 深度观察 S10E23, Zhang Haijun / 张海军 defines Scale Up less by cabinet boundary and more by whether software can run collective operations such as Reduce and All Gather across the domain as though it were one larger accelerator.

The concept links AI Cluster Networking to accelerator architecture. Scale Out networking connects many servers or clusters, while Scale Up tries to make the tightly coupled region fast enough that model parallelism and communication-heavy workloads do not leave chips idle.

Key Claims

• Scale Up is a system and software boundary, not only a physical rack boundary.
• The same supernode can span multiple cabinets if interconnect latency, bandwidth, and software abstraction make it behave as one domain.
• Copper links remain attractive at short range because latency, cost, and power are lower; optical links become more useful across cabinets or longer distances.
• Huawei’s UB route is framed as a unified protocol attempt across NPU, CPU, storage, Scale Up, and Scale Out, while Nvidia’s comparison stack uses NVLink and InfiniBand-style layers.
• Interconnect choice affects Token per Watt, cooling, model adaptation, and whether a supernode becomes useful capacity.

Connections

• AI Accelerator Supernode — system pattern Scale Up enables.
• AI Cluster Networking, Memory Wall, and High Bandwidth Memory — data movement and bandwidth context.
• Huawei CM384, Nvidia GB200 NVL72, and TPU Pod System Optimization — different pod or supernode-style system cases.
• Proprietary AI Interconnect Fragmentation — ecosystem risk when each vendor’s protocol is different.