HanaPino

Overview

HanaPino is the source-named OpenAI and Broadcom inference chip discussed in E251. The episode presents it as a relatively general inference accelerator that retains HBM and integrates different workload-specific blocks on one die.

Current Profile

The chip is framed as a power-first alternative to SRAM-heavy, system-level heterogeneity. It is said to cover prefill and decode, attention and feed-forward work, and small matrix multiplication while power-gating unused blocks as “dark silicon.” That choice can raise silicon cost but increase tokens produced within a fixed electricity envelope.

Key Characteristics

• Uses HBM rather than storing the full fixed model-weight working set in distributed SRAM.
• Places heterogeneous compute functions inside one chip instead of assigning them to separate chip types.
• Supports small-dimension matrix multiplication to improve small-batch inference behavior.
• Uses selective power gating or reduced activity in unused regions to prioritize energy efficiency.
• Is described as a general inference path with future training support, not a narrow decode-only accelerator.

Evidence

• Architecture and workload breadth: E251 says HanaPino covers multiple inference phases and even demonstrated non-LLM workloads.
• Memory and power tradeoff: E251 contrasts its HBM4 bandwidth and on-chip heterogeneity with SRAM-heavy multi-chip systems.
• Software path: E251 says kernels are written in a Wulong language and that Codex helped automate optimization.

Qualifications

The page reflects one podcast’s reading of public materials and a Hot Chips presentation. Launch date, nine-month development cycle, HBM bandwidth, Rubin comparison, Wulong/Codex workflow, and future training support have not been independently verified here and remain source-scoped.

What Changed

• Established the first canonical profile for HanaPino.
• Positioned the chip as a power-constrained, on-chip-heterogeneous counterpoint to SRAM-heavy inference systems.

Relationships

• OpenAI - model company identified by the source as the chip’s developer and intended user.
• Broadcom - implementation partner named in the source.
• High Bandwidth Memory - memory technology retained to provide capacity and bandwidth.
• Inference Decode Bandwidth - decode bottleneck addressed through HBM bandwidth and workload-specific blocks.
• AI Chip Specialization - specialization case that preserves broader workload coverage than a decode-only design.